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deltanedas ad691931c6 add memory cell and rework logic construction (#24983)
* rework construction to be deconstructable, add memory cell

* update textures

* add code

* add memory cell and ports, empty circuit

* d

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Co-authored-by: deltanedas <@deltanedas:kde.org>
2024-08-18 16:34:43 -06:00

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{
"version": 1,
"license": "CC-BY-SA-3.0",
"copyright": "or.png originally created by Kevin Zheng, 2022. All are modified by deltanedas (github) for SS14, 2024.",
"size": {
"x": 32,
"y": 32
},
"states": [
{
"name": "base"
},
{
"name": "logic"
},
{
"name": "or"
},
{
"name": "and"
},
{
"name": "xor"
},
{
"name": "nor"
},
{
"name": "nand"
},
{
"name": "xnor"
},
{
"name": "edge_detector"
},
{
"name": "or_icon"
},
{
"name": "power_sensor"
},
{
"name": "memory_cell"
}
]
}